The present application is based on application Nos. 10-333039 and 10-357732 filed in Japan, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to a data processing system, and more particularly, to a data processing system in which a plurality of serially connected processing portions execute respective parts of a series of processings asynchronously to input data.
2. Description of the Related Art
FIG. 44 is a block diagram showing the general configuration of a synchronous pipeline type data processing apparatus as a first conventional technique. The conventional data processing apparatus includes an MPU 70, an image input device 71, processing portions 72 to 76 to execute five processings, SH correction, Log conversion, MTF correction, gamma correction and binarization, respectively and an image output device 77. Image input device 71 includes a photoelectric conversion element such as CCD, a driving system operating the same, and an A/D converter, scans a document for example including both a continuous tone image and line drawing to generate a sampled analog signal, and quantizes the sampled analog signal using the A/D converter into continuous tone reflectivity data in which each pixel has 8 bits (256 tones), for output as a digital signal.
Processing portion 72 performs SH correction processing. The SH correction is also called xe2x80x9cshading correctionxe2x80x9d, and is a correction processing to remove reading variations (shading variations) caused by variations in the performance in the photoelectric conversion element such as CCD in image input device 71.
Processing portion 73 performs Log conversion processing. The Log conversion is a processing to calculate and output 8-bit continuous tone density data in the Log relation with the continuous tone reflectivity data after the SH correction.
Processing portion 74 performs MTF correction processing. The MTF correction is performed to correct sharpness, and the sharpness of the 8-bit continuous tone density data obtained by executing the Log conversion to image data at processing portion 73 is corrected using a digital filter such as a Laplacian filter.
Processing portion 75 performs gamma correction processing. The gamma correction is performed to correct the difference in the tone curve between image input device 71 and image output device 77 so as to realize a desired gamma characteristic for the entire data processing apparatus. For example, using an LUT (Look Up Table) of 256 words, 8 bits, non-linear gamma correction data is output. The gamma correction may be also performed to set a desired gamma characteristic for the operator.
Processing portion 76 performs binarizing processing. The binarizing is performed to convert 8-bit continuous tone density data subjected to the gamma correction into 1-bit binary data corresponding to the brightness. The binarizing processing employs area-type tone binarizing such as error diffusion binarizing.
Image output device 77 is a printer such as an electrophotographic printer or ink jet printer, and prints the 1-bit binary data formed by binarization at processing portion 76 onto an output medium such as paper.
Image input device 71, processing portions 72 to 76 and image output device 77 are connected through an image data bus, and process data input in synchronization with a pixel clock common to them.
Thus, in the synchronous pipeline type data processing apparatus described in conjunction with the first conventional technique, image data input from image input device 71 is sequentially processed by processing portions 72 to 76 on a pixel data piece basis. In order to achieve synchronism in exchange of the pixel data among image input device 71, processing portions 72 to 76, and image output device 77, a pixel clock corresponding to each piece of pixel data is generated by a clock generator (not shown), and image input device 71, processing portions 72 to 76, and image output device 77 operate in synchronization with the pixel clock.
As a second conventional technique, the five processings described in conjunction with the first conventional technique are executed asynchronously. FIG. 45 is a block diagram showing the asynchronous processing method. Referring to FIG. 45, processing blocks 80, 81 and 82 can perform processings in response to clocks 85, 86 and 87 specific to them. However, since the processing blocks operate without synchronization, data cannot be exchanged directly among the processing blocks. Thus, buffer memories 83 and 84 having a prescribed capacity are necessary among the blocks. This is because buffer memories 83 and 84 can absorb the difference in the processing speeds of processing blocks 80, 81 and 82.
Furthermore, as a third conventional technique, there is a parallel processing method in which the same processings are performed in parallel. For example, according to a technique disclosed by Japanese Patent Laying-Open No. 61-28164, provided is a pipeline processor having a plurality of image pipeline processors which are connected in a ring for parallel processing and task (image data), an object program for each task, and a table for each task are loaded from the memory to the pipeline processor. The pipeline processor processes prescribed tasks in parallel.
In the synchronous pipeline type data processing apparatus described in conjunction with the first conventional technique, image input device 71, processing blocks 72 to 76 and image output device 77 operate in synchronization with a pixel clock, and the pixel clock must be generated based on any element having the lowest operating speed among image input device 71, processing portions 72 to 76, and image output device 77. As a result, the circuit must be constructed according to a processing portion forming a bottleneck (having the lowest operating speed), which makes difficult the circuit design.
Furthermore, in the asynchronous processing type data processing apparatus described in conjunction with the second conventional technique, a processing block forming a bottleneck would not determine the processing speed of the data processing apparatus unlike the case of the synchronous pipeline method described in conjunction with the first conventional technique, but buffer memories are necessary, which pushes up the cost. In addition, since data is written/read to/from the buffer memory by two processing blocks, each block must accommodate such that one of the blocks can access a buffer memory, or such an arbitration processing must be performed by a controller provided for each of the buffer memories.
Furthermore, in the parallel processing method described in conjunction with the third conventional technique, a processing with a large processing load is processed by a plurality of processing blocks connected in parallel, and therefore high speed processing can be performed, but excess processing blocks to execute a processing with a large load are previously added. As a result, if the load of a processing block changes based on input data, one of processing blocks connected in parallel is not used when the load is small, which lowers the performance of the apparatus.
Also as a fourth conventional technique, an asynchronous type data processing apparatus to sequentially execute a plurality of processings to input data using a plurality of MPUs (micro processing units) is known. In the conventional data processing apparatus, the plurality of MPUs execute respective parts of the plurality of processings for asynchronous data processing, and data is exchanged among the MPUs to execute the series of processings to the input data.
FIG. 46 is a block diagram for use in illustration of data input/output between MPUs in the conventional data processing apparatus. The figure shows data input/output in executing 10 processings, processings 1 to 10 by two MPUs, MPUs 121 and 122. MPU 121 executes 5 processings, processings 1 to 5, while MPU 122 executes the succeeding 5 processings, processings 6 to 10. Therefore, data input to MPU 121 is subjected to the five processings, processings 1 to 5, and then transmitted to MPU 122, and MPU 122 executes processings 6 to 10 to the data processed by MPU 121.
Two control signals, request signal ACK and transmission signal REQ are transmitted/received between MPUs 121 and 122 to transmit data DATA. Request signal ACK is a signal to request data DATA, and transmitted from MPU 122 to MPU 121. Transmission signal REQ is a signal to transmit data DATA, and transmitted from MPU 121 to MPU 122.
When request signal ACK is transmitted from MPU 122 to MPU 121, the state of MPU 122 is that execution of processings 6 to 10 by MPU 122 to the previous data has been completed. When transmission signal REQ is transmitted from MPU 121 to MPU 122, the state of MPU 121 is that request signal ACK has been received from MPU 122, and that execution of processings 1 to 5 to data DATA to be transmitted has been completed.
Therefore, MPU 121 can transmit transmission signal REQ to MPU 122 on the condition that request signal ACK is received from MPU 122 and execution of processings 1 to 5 has been completed. Meanwhile, MPU 122 can transmit request signal ACK on the condition that execution of processings 6 to 10 by MPU 122 has been completed. Data DATA will be transmitted from MPU 121 to MPU 122 only if both conditions for MPUs 121 and 122 are satisfied.
FIG. 47 is a chart for use in illustration of change with time in the operation states of MPUs 121 and 122. In FIG. 47, the horizontal direction represents time, and the time elapses to the right in the figure. From the top, the state of MPU 121 and then the state of MPU 122 are shown. In the lowermost part, time for executing all the processings, processings 1 to 10 to input data A and input data B is shown.
MPU 121 executes processings 1 to 5 to input data A (A (1 to 5)), transmits transmission signal REQ to MPU 122, then immediately executes processings 1 to 5 to input data B (B (1 to 5)), and stands by until request signal ACK is received from MPU 122. When request signal ACK is received from MPU 122, MPU 121 transmits transmission signal REQ and transmits the processed input data B to MPU 122. Then, MPU 121 executes processings 1 to 5 to input data C.
After receiving transmission signal REQ from MPU 121, MPU 122 executes processings 6 to 10 to input data A (A (6 to 10) processed by MPU 121. When the processings to input data A is completed, MPU 122 transmits request signal ACK to MPU 121, and stands by until transmission signal REQ is received from MPU 121. Then, after receiving transmission signal REQ from MPU 121, MPU 122 receives input data B processed by MPU 121 and executes processings 6 to 10 to the received input data B (B (6 to 10)).
Since MPUs 121 and 122 thus execute respective processings, input data A and input data B are subjected to processings 1 to 10 in different time periods as shown in the figure.
In image processing to execute a plurality of processings to image data, loads for respective processings vary if pixel data in the image data varies. This is because difference in pixel data necessitates difference in the contents of processings. For example, in the image processing of executing 6 processings, i.e., shading correction, Log conversion, magnification changing, MTF correction, xcex3 correction, and binarization to image data including characters and photographs, the content of processing is different and therefore the load is different between the case in which pixel data to be processed belongs to the region of characters and the case in which it belongs to the region of photographs. Regarding MTF correction, if the load necessary for processing pixel data belonging to the character region is xe2x80x9c3xe2x80x9d, the load necessary for processing pixel data belonging to the photograph region is xe2x80x9c1xe2x80x9d. Regarding binarization, if the load necessary for processing pixel data belonging to the character region is xe2x80x9c1xe2x80x9d, the load necessary for processing pixel data belonging to the photograph region is xe2x80x9c3xe2x80x9d.
If the data processing apparatus according to the fourth conventional technique processes data such as image data whose load changes among processings, the load of MPU 121 and the load of MPU 122 are different depending upon the kind of data, and therefore the stand-by time before MPU 121 receives request signal ACK from MPU 122 and the stand-by time before MPU 122 receives data DATA are long, which disadvantageously lowers the processing speed.
The present invention was made in order to solve the above-mentioned problems, and it is one object of the present invention to devise the way of controlling asynchronous processing, and to provide a data processing system capable of processing data at a high speed even if the load changes depending upon data to be processed.
Another object of the present invention is to provide a data processing system capable of processing data at a high speed by reducing the entire stand-by time (waiting time) in which no operation is executed by a plurality of processing portions.
In order to achieve the above-described objects, a data processing system according to one aspect of the present invention includes a plurality of processors for executing a series of processings to data to be processed in a prescribed order, and a controller for determining the progress of a processing in each of the plurality of processors and changing a processing executed by each of the plurality of processors if there is a delayed processing, and processings by each of the processors are executed asynchronously.
According to another aspect of the present invention, a data processing system includes a plurality of processors for executing a series of processings to data to be processed in a prescribed order, and a controller for changing a processing executed by each of the plurality of processors based on the attribute of the data to be processed, and processings by a plurality of processors are executed asynchronously.
According to yet another aspect of the present invention, a data processing system includes a plurality of processors for executing a series of processings to data to be processed in a prescribed order, a memory for storing data processed by each of the plurality of processors, and a controller for determining the progress of a processing by each of the plurality of processors, controlling the plurality of processors such that data processed by each of the plurality of processors is transmitted to a succeeding processor without through the memory if there is no delayed processing, and if there is a delayed processing, data processed by a processor executing a processing preceding to the delayed processing is stored in the memory, and processings by the plurality of processors are executed asynchronously.
According to a still further aspect of the present invention, a data processing system includes a plurality of processors for executing a series of processings to data to be processed in a prescribed order, a memory for storing data processed by each of the plurality of processors, and a controller for, if one of the plurality of processors has no data to be processed and data that has been processed by the processor exists in the memory, instructing the one of the plurality of processors to execute a processing succeeding to a processing that has been executed by the processor and processings by the plurality of processors are executed asynchronously.
According to yet another aspect of the present invention, a data processing system includes a plurality of processors for executing a series of processings to data to be processed in a prescribed order, processings by the plurality of processors are executed asynchronously, and the plurality of processors include a first processor capable of executing a specified processing and a processing preceding to the specified processing among the series of processings, and a second processor capable of executing the specified processing and a processing succeeding to the specified processing.
According to yet another aspect of the present invention, a data processing system includes first and second processors for dividing a series of processings and executing the same to data to be processed in a prescribed order, processings by the plurality of processors are executed asynchronously, and at least a part of the series of processings can be executed by any of the first and second processors.
According to these aspects of the invention, the loads of the plurality of processors can be equalized even if the loads of the plurality of processors vary because of difference in data to be processed. As a result, data can be processed at a high speed, and a data processing system capable of high performance can be provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.